The present invention relates generally to semiconductor devices, and more specifically, to a semiconductor device including a gate channel having an adjusted threshold voltage.
Semiconductor devices, such as complimentary metal gate oxide semiconductor (CMOS) devices for example, include silicon germanium (SiGe) to adjust the threshold voltage (Vt). Regarding planar devices, the SiGe channel is epitaxially grown on the bulk or SOI silicon substrate and is patterned during gate or spacer definition. The junctions are then typically formed using in-situ doped SiGe in source/drain (S/D) and extension regions. Implanting a p-type dopant (e.g., boron) in the epitaxially grown SiGe results in very low diffusion of the species and leads to under lapped high-resistance extension regions. With respect to trigate/finFET devices, epitaxially growing SiGe entirely on the Si fins, including on upper surfaces of the fins in the S/D regions, leaves the entire core of the Si fins relatively undoped and results in high-access resistance.